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2 adc, 6 dac, 96 khz, 24-bit sigma-delta codec ad1839a rev. b in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . features 5 v st ereo au di o system with 3.3 v tolerant d i gital interface supports up to 96 khz sample rates 192 k hz s a mpl e rate a v ail a ble on 1 da c supports 16-/20-/24-bit word lengths multibit - ? m o dulators with perfect differe ntial lineari t y restoration for reduced idle tones and noise f l oor data-directed s c rambling dac sleast sens iti v e to jitter single-ended output adcs: ?95 db t h d + n, 105 db snr and dyna mic range dacs: ?92 db t h d + n, 108 db snr and dyna mic range on-chip volume controls per channel with 10 24-step lin ear scale dac and adc s o ftware co ntrollable clickle ss mutes digital de-emp hasis processing supports 256 f s , 512 f s , an d 768 f s mast er mode clocks po wer-do wn mo de and so ft p o wer-do wn mode flexible seria l data port with right-justified, left-justifi ed, i 2 s compatible, and ds p seria l modes tdm interface mode supports 8- in/8-out ope r ation using a single sharc? sport 52-lea d mqfp plastic package applications dvd vid e o and audio pla y ers home theater s y stems automotive a u dio systems audio / vis u al r e ceivers digital a u dio e ffects process gener a l description the ad1839a is a hig h p e r f o r ma nce sin g le-chi p co dec tha t fe a t ur es t h r e e ster e o d a cs an d o n e s t er e o a d c . e a ch d a c co m p r i s e s a h i g h p e r f o r ma n c e dig i t a l in t e r p ola t io n f i l t er , a m u l t ib i t -? mo d u l a t o r fe a t ur in g ana l og d e vi ces p a t e n t e d te ch nol o g y , and a c o n t i n u o u s - t i m e volt age - out an a l o g s e c t i o n . e a ch d a c h a s i n de p e n d e n t volum e con t r o l and click l ess m u te f u n c tio n s. the ad c com p r i s e s tw o 24-b i t con v ersio n c h a n n e ls wi t h m u l t ib i t - ? mo d u la to rs a nd de cim a t i on f i l t ers. the ad1839a als o co n t a i ns a n o n -c hi p r e f e r e nce wi th a n o minal val u e of 2.25 v . the ad1839a c o n t a i n s a f l exi b l e s e r i al in t e r f ac e tha t al lo ws gl ue l e s s co nn ec ti o n t o a va ri e t y o f d s p c h i p s , aes/ eb u r e cei v ers, a nd s a m p le ra te con v er t e rs. th e ad18 39a can b e co nf igur e d in le f t - j ust i f i e d , r i g h t- j u st if ie d , i 2 s, or ds p co m p a t i- b l e s e r i al m o des . c o n t r o l o f th e ad1839a is achiev e d b y m e a n s o f a n s p i? com p a t ib le s e r i al p o r t . w h ile t h e ad1839a can b e o p era t e d f r o m a sin g le 5 v s u p p l y , i t als o f e a t ur es a s e p a ra t e su p p ly p i n fo r i t s dig i t a l in ter f ac e t h a t a l lo ws t h e de vice to b e i n te r f a c e d to ot he r d e v i c e s u s i n g 3 . 3 v p o we r suppl i e s . t h e ad1839a is a v aila b l e in a 52 -le a d m q fp p a c kag e a nd is s p ecif ie d f o r th e ?40c t o +85c ind u s t r i al t e m p er a t ur e ra n g e . functional bloc k dia g ram outl1 control port clock filtd filtr adclp adcln adcrp adcrn dlrclk dbclk dsdata1 dsdata2 dsdata3 dauxdata mclk odvdd dvdd avdd avdd dvdd agnd dgnd cin clatch cclk cout digital filter digital filter m/s volume serial data i/o port digital filter v ref outr1 volume outl2 volume digital filter outr2 volume outl3 volume digital filter outr3 volume - ? adc aauxdata3 ad1839a asdata abclk alrclk agnd agnd agnd dgnd 03627-b - 001 - ? adc - ? dac - ? dac - ? dac pd/rst fi g u r e 1 .
ad1839a rev. b | page 2 of 24 table of contents specifications..................................................................................... 3 test conditions............................................................................. 3 timing specifications....................................................................... 5 absolute maximum ratings............................................................ 7 temperature range ...................................................................... 7 esd caution.................................................................................. 7 pin configuration and function descriptions............................. 8 typical performance characteristics ............................................. 9 terminology .................................................................................... 11 functional overview...................................................................... 12 adcs............................................................................................ 12 dacs ............................................................................................ 12 dac and adc coding.............................................................. 12 ad1839a clocking scheme ..................................................... 12 reset and power-down .......................................................... 13 power supply and voltage reference....................................... 13 serial control port ..................................................................... 13 serial data portsdata format............................................... 14 packed modes ............................................................................. 14 auxiliary time division multiplexing (tdm) mode ........... 14 control/status registers ............................................................ 19 cascade mode............................................................................. 22 outline dimensions ....................................................................... 24 ordering guide .......................................................................... 24 revision history 5/04data sheet changed from rev. a to rev. b updated format universal changes to data sheet title1 2/04data sheet changed from rev. 0 to rev. a changes to ordering guide ............................................................. 6 deleted clock signals section ....................................................... 11 added ad1835a clocking scheme section................................ 11 added table ii and table iii and renumbered following tables 11 changes to auxiliary (tdm mode) section................................ 13 changes to figure 5......................................................................... 14 changes to figure 6......................................................................... 14 added figures 7a and 8a................................................................. 15 renamed figure 7 and figure 8 to figure 7b and figure 8b ..... 15 changes to figure 9......................................................................... 15 changes to table viii ..................................................................... 21 updated outline dimensions ........................................................ 24
ad1839a rev. b | page 3 of 24 specifications test conditions supply voltages 5.0 v (avdd, dvdd) ambient temperature 25c input clock 12.288 mhz (256 f s mode) dac input signal 1.0078125 khz, 0 dbfs adc input signal 1.0078125 khz, ? 1 dbfs input sample rate (f s ) 48 khz measurement bandwidth 0 hz to 20 khz word width 24 bits load capacitance 100 pf load impedance 47 k? performance of all channels is identical (except for the interchannel gain mismatch and interchannel phase deviation specificat ions). table 1. parameter min typ max unit analog-to-digital converters adc resolution 24 bits dynamic range (20 hz to 20 khz, C60 db input) no filter 103 db a-weighted (48 khz and 96 khz) 100 105 db total harmonic distortion + noise (thd + n) 48 khz C95 C88.5 db 96 khz C95 C87.5 db interchannel isolation 100 db interchannel gain mismatch 0.025 db analog inputs differential input range (full scale) C2.828 +2.828 v common-mode input voltage 2.25 v input impedance 4 k? input capacitance 15 pf v ref 2.25 v dc accuracy gain error 5 % gain drift 35 ppm/c digital-to-analog converters dac resolution 24 bits dynamic range (20 hz to 20 khz, C60 dbfs input) no filter 103 105 db a-weighted filter (48 khz and 96 khz) 105 108 db total harmonic distortion + noise (48 khz and 96 khz) C92 C90 db interchannel isolation 110 db dc accuracy gain error 4 % interchannel gain mismatch 0.025 db gain drift 200 ppm/c interchannel phase deviation 0.1 degrees volume control step size (1023 linear steps) 0.098 % volume control range (maximum attenuation) 60 db mute attenuation C100 db de-emphasis gain error 0.1 db full-scale output voltage at each pin (single-ended) 1.0 (2.8) v rms (v p-p) output resistance at each pin 180 ? common-mode output voltage 2.25 v
ad1839a rev. b | page 4 of 24 parameter min typ max unit adc decimation filter, 48 khz 1 pass band 21.77 khz pass-band ripple 0.01 db stop band 26.23 khz stop-band attenuation 120 db group delay 910 s adc decimation filter, 96 khz 1 pass band 43.54 khz pass-band ripple 0.01 db stop band 52.46 khz stop-band attenuation 120 db group delay 460 s dac interpolation filter, 48 khz 1 pass band 21.77 khz pass-band ripple 0.01 db stop band 28 khz stop-band attenuation 55 db group delay 340 s dac interpolation filter, 96 khz 1 pass band 43.54 khz pass-band ripple 0.01 db stop band 52 khz stop-band attenuation 55 db group delay 160 s dac interpolation filter, 192 khz 1 pass band 81.2 khz pass-band ripple 0.06 db stop band 97 khz stop-band attenuation 80 db group delay 110 s digital i/o input voltage high 2.4 v input voltage low 0.8 v output voltage high odvdd C 0.4 v output voltage low 0.4 v leakage current 10 a power supplies supply voltage (avdd and dvdd) 4.5 5.0 5.5 v supply voltage (odvdd) 3.0 dvdd v supply current i analog 84 95 ma supply current i analog , power-down 55 67 ma supply current i digital 64 74 ma supply current i digital , power-down 1 4.5 ma dissipation operation, both supplies 740 mw operation, analog supply 420 mw operation, digital supply 320 mw power-down, both supplies 280 mw power supply rejection ratio 1 khz, 300 mv p-p signal at analog supply pins C70 db 20 khz, 300 mv p-p signal at analog supply pins C75 db 1 guaranteed by design.
ad1839a rev. b | page 5 of 24 timing specifications table 2. parameter min max unit comments master clock and reset t mh mclk high 15 ns t ml mclk low 15 ns t pdr pd / rst low 20 ns spi port t cch cclk high 40 ns t ccl cclk low 40 ns t ccp cclk period 80 ns t cds cdata setup 10 ns to cclk rising edge t cdh cdata hold 10 ns from cclk rising edge t cls clatch setup 10 ns to cclk rising edge t clh clatch hold 10 ns from cclk rising edge t coe cout enable 15 ns from clatch falling edge t cod cout delay 20 ns from cclk falling edge t cots cout three-state 25 ns from clatch rising edge dac serial port (48 khz and 96 khz) normal mode (slave) t dbh dbclk high 60 ns t dbl dbclk low 60 ns f db dbclk frequency 64 f s t dls dlrclk setup 10 ns to dbclk rising edge t dlh dlrclk hold 10 ns from dbclk rising edge t dds dsdata setup 10 ns to dbclk rising edge t ddh dsdata hold 10 ns from dbclk rising edge packed 128/256 modes (slave) t dbh dbclk high 15 ns t dbl dbclk low 15 ns f db dbclk frequency 256 f s t dls dlrclk setup 10 ns to dbclk rising edge t dlh dlrclk hold 10 ns from dbclk rising edge t dds dsdata setup 10 ns to dbclk rising edge t ddh dsdata hold 10 ns from dbclk rising edge adc serial port (48 khz and 96 khz) normal mode (master) t abd abclk delay 25 ns from mclk rising edge t ald alrclk delay 5 ns from abclk falling edge t abdd asdata delay 10 ns from abclk falling edge normal mode (slave) t abh abclk high 60 ns t abl abclk low 60 ns f ab abclk frequency 64 f s t als alrclk setup 5 ns to abclk rising edge t alh alrclk hold 15 ns from abclk rising edge t abdd asdata delay 15 ns from abclk falling edge packed 128/256 mode (master) t pabd abclk delay 40 ns from mclk rising edge t pald lrclk delay 5 ns from abclk falling edge t pabdd asdata delay 10 ns from abclk falling edge
ad1839a r e v. b | pa ge 6 o f 2 4 p a r a m e t e r m i n m a x u n i t c o m m e n t s tdm256 mode (master, 48 khz and 96 khz) t tbd b c l k d e l a y 40 ns from mclk risin g edge t fs d fstdm d e l a y 5 ns from bclk risin g edge t ta bd d a s d a t a d e l a y 10 ns from bclk risin g edge t t dds dsdata1 se tup 15 ns to bclk falling edge t t ddh dsdata1 hold 15 ns from bclk falling edge tdm256 mode (slave, 48 khz and 96 khz) f ab bclk frequency 256 f s t tbc h b c l k h i g h 1 7 n s t tbc l b c l k l o w 1 7 n s t tfs fstdm set u p 10 ns to bclk falling edge t tfh fstdm hold 10 ns from bclk falling edge t tbd d asdata delay 15 ns from bclk rising edge t t dds dsdata1 se tup 15 ns to bclk falling edge t t ddh dsdata1 hold 15 ns from bclk falling edge tdm512 mode (master, 48 khz) t tbd bclk delay 40 ns from mclk rising edge t fs d fstdm delay 5 ns from bclk risin g edge t ta bd d asdata delay 10 ns from bclk rising edge t t dds dsdata1 se tup 15 ns to bclk falling edge t t ddh dsdata1 hold 15 ns from bclk falling edge tdm512 mode (slave, 48 khz) f ab bclk frequency 512 f s t tbc h b c l k h i g h 1 7 n s t tbc l b c l k l o w 1 7 n s t tfs fstdm set u p 10 ns to bclk falling edge t tfh fstdm hold 10 ns from bclk falling edge t tbd d asdata delay 15 ns from bclk rising edge t t dds dsdata1 se tup 15 ns to bclk falling edge t t ddh dsdata1 hold 15 from bclk falling edge auxilia r y in te rface (48 khz and 96 khz) t ax ds aauxdata set u p 10 ns to auxbclk rising edge t ax dh aauxdata hold 10 ns from auxbclk rising edge t dx d dauxdata delay 10 ns from auxbclk falling edge f abp auxbclk frequency 64 f s n s sl ave mode t ax bh a u x b c l k h i g h 1 5 n s t ax bl a u x b c l k l o w 1 5 n s t ax ls auxlrclk set u p 10 ns to auxbclk rising edge t ax lh auxlrclk hold 10 ns from auxbclk rising edge mas t er mode t aux b clk auxbclk delay 20 ns from mclk rising edge t aux l rclk auxlrclk delay 15 ns from auxbclk falling edge mclk 03627-b - 002 t pdr t ml t mh t mclk pd/rst fi g u r e 2 . m c l k a n d pd / rst ti min g
ad1839a r e v. b | pa ge 7 o f 2 4 absolute maximum ratings t a = 2 5 c , u n l e ss ot he r w i s e not e d. table 3. p a r a m e t e r r a t i n g avdd, dvdd, odvdd to ag nd, dgnd ?0.3 v to +6.0 v agnd to dg nd ?0.3 v to +0.3 v digital i/o voltage to dgnd ?0.3 v to odvd d + 0.3 v analog i/o voltage to agnd ?0.3 v to avdd + 0.3 v operating tem p erature range industrial (a ver s ion) ?40c to +85c temperature range table 4. p a r a m e t e r m i n t y p m a x u n i t specification s g u aranteed +25 c functionality guaranteed ?40 +85 c s t o r a g e ? 6 5 + 1 5 0 c s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . this is a s t r e s s r a t i ng o n ly ; f u nc t i on a l op e r a t i o n of t h e d e v i c e a t t h e s e or a n y o t h e r con d i t io ns a b o v e t h os e list e d i n t h e o p era t io nal s e c t io n s o f t h is sp e c if ic a t io n is n o t i m pli e d . e x p o sur e t o a b s o l u t e max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vice r e l i ab i l i t y . esd caution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
ad1839a r e v. b | pa ge 8 o f 2 4 pin conf iguration and fu nction descriptions 03627-b - 003 52 dgnd 51 cclk 50 cout 49 as data 48 odvdd 47 mclk 46 alrclk 45 abclk 44 aaux data3 43 ds data3 42 ds data2 41 ds data1 40 dgnd 38 dbclk 37 dlrclk 36 dauxdata 33 nc 34 agnd 35 m/s 39 dvdd 32 nc 31 nc 30 agnd 28 outr3 27 nc 29 avdd 2 clatch 3 cin 4 pd/rst 7 outl1 6 nc 5 agnd 1 dvdd 8 nc 9 outr1 10 agnd 12 nc 13 outl2 11 avdd nc = no connect 14 nc 15 outr2 16 agnd 17 filtd 18 filtr 19 av dd 20 adcln 21 adclp 22 adcrn 23 adcrp 24 agnd 25 nc 26 outl3 ad1839a top view (not to scale) f i gure 3. pin config ur ation ta ble 5. pi n f u nct i on d e s c ri pt i o ns pin no. mnemonic input/output description 1, 39 dvdd digital power supply. connect to digital 5 v su pply. 2 clatch i latch input for control data. 3 cin i serial control input. 4 pd / rst i p o w e r - d o w n/r e s e t . 5, 10, 16, 24, 30, 34 agnd analog ground. 6, 8, 12, 14, 25, 2 7 , 31C33 nc not connected. 7, 13, 26 outlx o dacx right channel negative output. 9, 15, 28 outrx o dacx right channel positive output. 11, 19, 29 avdd analog power s u pply. connect to analog 5 v supply. 17 filtd filter capacitor connection. recommended 10 f/100 nf. 1 8 f i l t r reference filter capacitor connection. recomm ended 10 f/100 nf. 20 adcln i adc left channel negative input. 21 adclp i adc left channel positive input . 22 adcrn i adc right channel negative input. 23 adcrp i adc right channel positive input. 35 m /s i adc m a ster/sla ve select. 36 dauxdat a o aux i liary dac output data. 37 dlrclk i/o dac lr clock. 38 dbclk i/o dac bit clock. 40, 52 dgnd digital ground. 41C43 dsdatax i dacx input data (l eft and right channel s ) . 44 aauxdata3 i auxiliary adc3 digital input. 45 abclk i/o adc bit clock. 46 alrclk i/o adc lr clock. 47 mclk i master clock in put. 48 odvdd digital output driver power supply. 49 asdata o adc serial data output. 50 cout o output for cont rol data. 51 cclk i control clock input for control data.
ad1839a r e v. b | pa ge 9 o f 2 4 typical perf orm ance cha r acte ristics 03627-b - 004 frequency (normalized to f s ) 0 5 10 15 magnitude (db) 0 ?50 ?100 ?150 f i gure 4. adc comp osite f i lter respon se 03627-b - 005 frequency (hz) 02 0 51 0 1 5 magnitude (db) ?3 0 ?2 5 ?2 0 ?1 5 ?1 0 ?5 0 5 f i gur e 5 . adc h i gh-p a ss f i l t er resp o n se , f s = 4 8 kh z 03627-b - 006 frequency (normalized to f s ) 0 2.0 0.5 1.0 1.5 magnitude (db ) ?150 0 ?100 ?5 0 f i g u re 6. a d c co m p os it e f i lt er r e s p on s e (p as s-band s e c t i o n) 03627-b - 007 frequency (hz) 02 51 0 1 5 magnitude ( d b) ?30 ?25 ?20 ?15 ?10 ?5 0 5 0 f i gur e 7 . adc h i gh-p a ss f i l t er resp o n se , f s = 9 6 kh z 03627-b - 008 frequency ( khz) 200 0 50 100 150 magnitude (db) ?150 0 ?50 ?100 fi g u r e 8 . d a c c o m p o s i t e fi l t e r r e s p o n s e , f s = 4 8 kh z 03627-b - 009 frequency ( khz) 200 0 magnitude (db) 0 ?50 ?150 ?100 50 100 150 fi g u r e 9 . d a c c o m p o s i t e fi l t e r r e s p o n s e , f s = 9 6 kh z
ad1839a rev. b | page 10 of 24 03627-b - 010 frequency ( khz) 200 0 5 0 100 150 magnitude (db) 0 ?50 ?100 ?150 f i gure 10. d a c comp os it e f i lt er response , f s = 19 2 k h z 03627-b - 011 frequency ( khz) 20 0 magnitude (db) 0.10 0.05 ? 0.10 0 ? 0.05 51 0 1 5 f i gure 11. d a c comp os it e f i lt er response , f s = 48 kh z (p ass- band s e c t ion) 03627-b - 012 frequency ( khz) 50 0 10 20 30 40 magnitude (db) 0.2 0.1 ?0.2 0 ?0.1 f i gure 12. d a c comp os it e f i lt er response , f s = 96 kh z (p ass- band s e c t ion) 03627-b - 013 frequency (khz) 100 0 magnitude (db) 0.10 0.05 ? 0.10 0 ? 0.05 20 40 60 80 f i gure 13. d a c comp os it e f i lt er response , f s = 19 2 k h z ( p as s-b a nd s e c t ion)
ad1839a rev. b | page 11 of 24 terminology dynamic range the ratio of a full-scale input signal to the integrated input noise in the pass band (20 hz to 20 khz), expressed in decibels. dynamic range is measured with a ?60 db input signal and is equal to (s/[thd + n]) + 60 db. note that spurious harmonics are below the noise with a ?60 db input, so the noise level establishes the dynamic range. the dynamic range is specified with and without an a-weight filter applied. signal-to-(total harmonic distortion + noise) [s/(thd + n)] the ratio of the root-mean-square (rms) value of the fundamental input signal to the rms sum of all other spectral components in the pass band, expressed in decibels. pass band the region of the frequency spectrum unaffected by the attenuation of the digital decimators filter. pass-band ripple the peak-to-peak variation in amplitude response from equal- amplitude input signal frequencies within the pass band, expressed in decibels. stop band the region of the frequency spectrum attenuated by the digital decimators filter to the degree specified by stop-band attenuation. gain error with identical near full-scale inputs, the ratio of actual output to expected output, expressed as a percentage. interchannel gain mismatch with identical near full-scale inputs, the ratio of outputs of the two stereo channels, expressed in decibels. gain drift change in response to a near full-scale input with a change in temperature, expressed as parts-per-million (ppm) per c. crosstalk (eiaj method) ratio of response on one channel with a grounded input to a full-scale 1 khz sine wave input on the other channel, expressed in decibels. power supply rejection with no analog input, signal present at the output when a 300 mv p-p signal is applied to the power supply pins, expressed in decibels of full scale. group delay intuitively, the time interval required for an input pulse to appear at the converters output, expressed in microseconds. more precisely, the derivative of radian phase with respect to the radian frequency at a given frequency. group delay variation the difference in group delays at different input frequencies. specified as the difference between the largest and the smallest group delays in the pass band, expressed in microseconds. acronyms adc analog-to-digital converter. dac digital-to-analog converter. dsp digital signal processor. imclk internal master clock signal used to clock the adc and dac engines. mclk external master clock signal applied to the ad1839a.
ad1839a rev. b | page 12 of 24 functional overview adcs there are two adc channels in the ad1839a, configured as a stereo pair. each adc has fully differential inputs. the adc section can operate at a sample rate of up to 96 khz. the adcs include on-board digital decimation filters with 120 db stop- band attenuation and linear phase response, operating at an oversampling ratio of 128 (for 48 khz operation) or 64 (for 96 khz operation). the peak level information for each adc may be read from the adc peak 0 and adc peak 1 registers. the data is supplied as a 6-bit word with a maximum range of 0 db to ? 63 db and a resolution of 1 db. the registers hold peak information until read; after reading, the registers are reset so that new peak information can be acquired. (refer to the register description in table 10 for details of the format.) the two adc channels have a common serial bit clock and a left-right framing clock. the clock signals are all synchronous with the sample rate. the adc digital pins, abclk and alrclk, can be set to operate as inputs or outputs by connecting the m /s pin to odvdd or dgnd, respectively. when the pins are set as outputs, the ad1839a generates the timing signals. when the pins are set as inputs, the timing must be generated by the external audio controller. dacs the ad1839a has six dac channels arranged as three independent stereo pairs, with six single-ended analog outputs. each channel has its own independently programmable attenuator, adjustable in 1,024 linear steps. digital inputs are supplied through three serial data input pins (one for each stereo pair) and a common frame (dlrclk) and bit clock (dbclk). alternatively, one of the packed data modes can be used to access all six channels on a single tdm data pin. a stereo replicate feature is included where the dac data sent to the first dac pair is also sent to the other dacs in the part. the ad1839a can accept dac data at a sample rate of 192 khz on dac 1 only. the stereo replicate feature can then be used to copy the audio data to the other dacs. each of the output pins sits at a dc level of v ref and swings 1.4 v for a 0 db digital input signal. a single op amp, third- order, external low-pass filter is recommended to remove high frequency noise present on the output pins. note that the use of op amps with low slew rate or low bandwidth may cause high frequency noise and tones to fold down into the audio band; care should be exercised in selecting these components. the filtd pin should be connected to an external grounded capacitor. this pin reduces the noise of the internal dac bias circuitry, thus reducing the dac output noise. at times, this capacitor may be eliminated with little effect on performance. dac and adc coding the dac and adc output data stream is in a twos complement encoded format. a 16-bit, 20-bit, or 24-bit word width can be selected. the coding scheme is detailed in table 6. table 6. coding scheme code level 01111......1111 +fs 00000......0000 0 (ref level) 10000......0000 ?fs ad1839a clocking scheme by default, the ad1839a requires an mclk signal that is 256 times the required sample frequency up to a maximum of 12.288 mhz. the ad1839a uses a clock scaler to double the clock frequency for use internally. the default setting of the clock scaler is multiply by 2. the clock scaler can also be set to multiply by 1 (bypass) or multiply by 2/3. the clock scaler is controlled by programming the bits in the adc control 3 register. the internal mclk signal, imclk, should not exceed 24.576 mhz to ensure correct operation. the mclk of the ad1839a should remain constant during normal operation of the dac and adc. if it is required to change the mclk rate, the ad1838a should be reset. also, if mclk scaler needs to be modified so that the imclk does not exceed 24.576 mhz, this should be done during the internal reset phase of the ad1839a by programming the bits in the first 3,072 mclk periods following the reset. selecting the dac sampling rate the ad1839a dac engine has a programmable interpolator that allows the user to select different interpolation rates based on the required sample rate and mclk value available. table 7 shows the settings required for sample rates based on a fixed mclk of 12.288 mhz. table 7. dac sample rate settings sample rate interpolator rate dac control 1 register 48 khz 8 000000xxxxxxxx00 96 khz 4 000000xxxxxxxx01 192 khz 2 000000xxxxxxxx10 selecting an adc sample rate the ad1839a adc engine has a programmable decimator that allows the user to select the sample rate based on the mclk value. by default, the output sample rate is imclk/512. to achieve a sample rate of imclk/256, the sample rate bit in the adc control 1 register should be set as shown in table 8. table 8. adc sample rate settings sample rate adc control 1 register imclk/512 1100000xx0xxxxxx (48 khz) imclk/256 1100000xx1xxxxxx (96 khz)
ad1839a rev. b | page 13 of 24 t o m a in ta i n t h e h i gh es t pe rf o r m a n c e pos s i b l e , th e c l oc k ji t t er o f t h e mast er clo c k sig n al s h o u ld b e limi t e d t o les s t h a n 300 ps r m s, m e as ur ed usin g t h e ed g e -t o-edge t e c h niq u e . e v en a t t h es e l e v e l s, ext r a n o i s e o r t o n e s ma y a p p e a r i n t h e d a c o u t p u t s if th e ji t t er s p ec tr um co n t a i n s l a rg e s p ec tral p e aks. i t is hig h l y re c o m m e nd e d t h a t t h e m a ste r c l o c k b e ge ne r a t e d b y an i n d e - p e nden t cr ys tal os cil l a t o r . i n addi tion, i t is esp e cial l y im p o r t a n t tha t t h e c l o c k sig n al n o t be p a s s ed thr o ug h an f p ga o r o t h e r la rg e dig i tal c h i p bef o r e bein g a p p l ied t o t h e ad1839a. i n m o s t cas e s, this ind u c e s c l o c k ji t t e r be ca us e t h e c l o c k sig n al is s h a r in g co m m o n p o w e r a nd g r o u nd conn e c t i o n s wi t h unr e la te d dig i t a l o u t p u t sig n als. reset and power-down pd / rs t p o w e rs do wn t h e chi p and s e ts t h e con t r o l r e g i s t ers to t h e i r de f a u l t s e t t i n g s . a f te r pd / rs t is de ass e r t e d , a n ini t ia l- iz a t io n r o u t ine r u n s in side t h e de vice t o cle a r a l l m e m o r i es t o zer o . t h e in i t ia l i z a t i o n lasts a p pr o x ima t e l y 20 lrclk i n ter v a l s. dur i n g this time , i t is r e co mm en de d tha t n o s p i wr i t es o c c u r . power supply and voltage ref e rence the ad1839a is desig n e d f o r 5 v s u p p lies. s e p a ra t e p o w e r s u pp l y pi ns are prov i d e d f o r t h e an a l o g an d d i g i t a l s e c t i o ns . th es e p i n s sh o u ld be b y p a s s e d wi t h 100 nf cer a mic c h i p c a p a c i tors , a s cl o s e to t h e pi ns a s p o ss ibl e , to m i ni mi z e noi s e p i c k u p . a b u l k a l umin u m e l ec trol ytic ca p a ci t o r o f a t leas t 22 f shou l d a l s o b e prov i d e d o n t h e s a me pc b o a r d a s t h e co de c. f o r cr i t ica l a p plic a t i o n s , im p r o v e d p e r f o r ma n c e is ob t a i n e d w i t h se pa ra t e s u p p li es f o r th e a n alog a n d d i g i tal s e ctio n s . i f th i s i s n o t p o ssi b le, i t i s r e co mme n d e d t h a t t h e a n a l o g a nd dig i t a l s u p p lies b e is ol a t e d b y t w o fer r i t e b e ads in s e r i es wi t h t h e b y p a ss c a p a c i tor of e a ch su p p ly . i t is im p o r t an t t h a t t h e ana l o g su p p ly b e as cl e a n as p o ss ibl e . the i n t e r n al v o l t a g e r e fer e n c e is b r o u g h t o u t on t h e fil t r p i n a nd sh o u ld b e b y p a ss e d as clos e as p o ssib le t o t h e ch i p , wi t h a p a ral l e l co m b ina t io n o f 10 f and 100 nf . the r e f e r e n c e v o l t a g e ma y b e u s e d to b i a s e x te r n a l op am p s to t h e c o mmon- m o d e v o l t a g e o f t h e analog in p u t and o u t p u t sig n al p i n s . th e c u r r en t dr a w n f r o m t h e v ref p i n sh o u ld be limi te d t o les s tha n 50 a. serial control port the ad1839a has a n s p i com p a t ib le co n t r o l p o r t t o p e r m i t p r og ra mmin g t h e i n t e r n al con t r o l r e g i s t ers fo r t h e ad c s an d d a cs, an d fo r r e adin g t h e ad c sig n a l le vels f r o m t h e i n t e r n a l p e ak det e c t o r s. the s p i p o r t is a 4-wir e s e r i al c o n t r o l p o r t . the f o r m a t is similar t o th e m o t o r o l a s p i f o r m a t excep t t h e in p u t d a t a -w o r d is 16 b i ts w i de. t h e max i m u m s e r i a l b i t clo c k f r eq uen c y is 12.5 mh z and ma y be com p lete l y asyn chr o n o us t o th e sa m p le ra t e o f th e ad c s a n d d a c s . f i gur e 15 s h o w s t h e f o r m a t o f th e s p i sig n al . clock scaling 1 2 2/3 mclk 12.288mhz dac input adc output dac engine interpolation filter - ? modulator dac 48khz/96khz/192khz 48khz/96khz analog output analog input imclk = 24.576mhz 03627-b - 014 adc engine optional hpf decimator/ filter - ? modulator f i gure 14. modu la r clo c k i ng s c h e m e clatch cclk cin cout d0 d8 d0 d15 d14 d9 d8 t cch t ccl d9 t cds t cdh t cls t clh t cod t cots t ccp t coe 03627-b - 015 f i gure 15. f o rm at o f spi ti ming
ad1839a rev. b | page 14 of 24 serial data portsdata format the adc serial data output mode defaults to the popular i 2 s format, where the data is delayed by 1 bclk interval from the edge of the lrclk. by changing bits 6 to 8 in adc control register 2, the serial mode can be changed to right-justified (rj), left-justified dsp (dsp), or left-justified (lj). in the rj mode, it is necessary to set bits 4 and 5 to define the width of the data-word. the dac serial data input mode defaults to i 2 s. by changing bits 5, 6, and 7 in dac control register 1, the mode can be changed to rj, dsp, lj, or packed mode 256. the word width defaults to 24 bits but can be changed by reprogramming bits 3 and 4 in dac control register 1. packed modes the ad1839a has a packed mode that allows a dsp or other controller to write to all dacs and read all adcs using one input data pin and one output data pin. packed mode 256 refers to the number of bclks in each frame. the lrclk is low while data from a left-channel dac or adc is on the data pin; lrclk is high while data from a right-channel dac or adc is on the data pin. dac data is applied on the dsdata1 pin, and adc data is available on the asdata pin. figure 19 to figure 24 show the timing for the packed mode. packed mode is available for 48 khz and 96 khz. auxiliary time division multiplexing (tdm) mode a special auxiliary mode is provided to allow three external stereo adcs and one external stereo dac to be interfaced to the ad1839a to provide 8-in/8-out operation. in addition, this mode supports a glueless interface to a single sharc dsp serial port, allowing a sharc dsp to access all eight channels of analog i/o. in this special mode, many pins are redefined; see table 9 for a list of redefined pins. the auxiliary and tdm interfaces are independently configurable to operate as masters or slaves. when the auxiliary interface is set as a master, by programming the auxiliary mode bit in adc control register 2, auxlrclk and auxbclk are generated by the ad1839a. when the auxiliary interface is set as a slave, auxlrclk and auxbclk need to be generated by an external adc, as shown in figure 27. the tdm interface can be set to operate as a master or slave by connecting the m /s pin to dgnd or odvdd, respectively. in master mode, the fstdm and bclk signals are outputs and are generated by the ad1839a. in slave mode, the fstdm and bclk are inputs and should be generated by the sharc. both 48 khz and 96 khz operations are available (based on a 12.288 mhz or 24.576 mhz mclk) in this mode. table 9. pin function changes in auxiliary mode pin name i 2 s mode auxiliary mode asdata (o) i 2 s data out, internal adc tdm data out to sharc. dsdata1 (i) i 2 s data in, internal dac1 td m data in from sharc. dsdata2 (i)/aauxdata1 (i) i 2 s data in, internal dac2 aux-i 2 s data in 1 (from external adc). dsdata3 (i)/aauxdata2 (i) i 2 s data in, internal dac3 aux-i 2 s data in 2 (from external adc). aauxdata3 (i) not connected aux-i 2 s data in 3 (from external adc). alrclk (o) lrclk for adc tdm frame sync out to sharc (fstdm). abclk (o) bclk for adc tdm bclk out to sharc. dlrclk (i)/auxlrclk (i/o) lrclk in/out internal dacs aux lrclk in/out. driven by extern al lrclk from adc in slave mode. in master mode, driven by mclk/512. dbclk (i)/auxbclk (i/o) bclk in/out internal dacs aux bclk in/out. driven by extern al bclk from adc in slave mode. in master mode, driven by mclk/8. dauxdata (o) not connected aux-i 2 s data out (to external dac).
ad1839a rev. b | page 15 of 24 lrclk bclk sdata lrclk bclk sdata lrclk bclk sdata lrclk bclk sdata left channel right channel left channel right channel left channel right channel msb msb msb msb msb msb msb msb lsb lsb lsb lsb lsb lsb lsb lsb left-justified mode ?16 bits to 24 bits per channel i 2 s mode ?16 bits to 24 bits per channel right-justified mode ?select number of bits per channel dsp mode ?16 bits to 24 bits per channel notes 1. dsp mode does not identify channel. 2. lrclk 3. bclk frequency is normally 64 lrclk but may be operated in burst mode. 03627-b - 016 1/ f s normally operates at f s except for dsp mode, which is 2 f s . f i gu r e 1 6 . s t er eo ser i a l mo de s abclk alrclk asdata left-justified mode asdata right-justified mode lsb asdata i 2 s compatible mode msb msb ? 1 msb msb 03627-b - 017 t abh t abl t als t abdd f i g u re 17. a d c s e r i al m o de tim i ng
ad1839a rev. b | page 16 of 24 dbclk dlrclk dsdata left-justified mode dsdata right-justified mode lsb dsdata i 2 s compatible mode msb msb ? 1 msb msb 03627-b - 018 t dbh t dbl t ddh t ddh t dds t dds t dlh t ddh t dds t ddh t dds t dls f i g u re 18. da c s e r i al m o de tim i ng lrclk bclk adc data slot 1 left 1 slot 2 left 2 slot 5 right 1 slot 6 right 2 msb msb ? 1 msb ? 2 16 bclks slot 3 left 3 slot 4 left 4 slot 7 right 3 slot 8 right 4 03627-b - 019 128 bclks f i g u re 19. a d c p a c k ed m o d e 1 2 8 lrclk bclk adc data slot 1 left 1 slot 2 left 2 slot 5 right 1 slot 6 right 2 msb msb ? 1 msb ? 2 32 bclks slot 3 left 3 slot 4 left 4 slot 7 right 3 slot 8 right 4 03627-b - 020 256 bclks f i g u re 20. a d c p a c k ed m o d e 2 5 6
ad1839a rev. b | page 17 of 24 lrclk bclk dac data slot 1 left 1 slot 2 left 2 slot 5 right 1 slot 6 right 2 msb msb ? 1 msb ? 2 16 bclks slot 3 left 3 slot 4 left 4 slot 7 right 3 slot 8 right 4 03627-b - 021 128 bclks f i g u re 21. da c p a c k ed m o d e 1 2 8 lrclk bclk dac data slot 1 left 1 slot 2 left 2 slot 5 right 1 slot 6 right 2 msb msb ? 1 msb ? 2 32 bclks slot 3 left 3 slot 4 left 4 slot 7 right 3 slot 8 right 4 03627-b - 022 256 bclks f i g u re 22. da c p a c k ed m o d e 2 5 6 abclk alrclk asdata msb msb ? 1 t abdd 03627-b - 024 t abh t abh t abl t alh f i g u re 23. a d c p a c k ed m o d e tim i ng dbclk dlrcl k dsdata msb msb ? 1 03627-b - 025 t dbh t ddh t dds t dbl t dls t dlh f i g u re 24. da c p a c k ed m o d e tim i ng
ad1839a rev. b | page 18 of 24 fstdm internal adc l1 aux_adc l2 aux_adc l3 aux_adc l4 internal adc r1 aux_adc r2 aux_adc r3 aux_adc r4 internal dac l1 internal dac l2 internal dac l3 internal dac r1 internal dac r2 internal dac r3 left right i 2 s - msb left bclk tdm asdata1 tdm (out) asdata dsdata1 tdm (in) dsdata1 aux lrclk i 2 s (from aux adc no. 1) aux bclk i 2 s (from aux adc no. 1) aauxdata1 (in) (from aux adc no. 1) aauxdata2 (in) (from aux adc no. 2) aauxdata3 (in) (from aux adc no. 3) auxbclk frequency is 64 frame rate; tdm bclk frequency is 256 frame rate. tdm inte rface aux - i 2 s inte rface msb tdm msb tdm i 2 s - msb left i 2 s - msb left i 2 s - msb right i 2 s - msb right i 2 s - msb right internal dac l4 internal dac r4 msb tdm msb tdm 1st ch 1st ch 8th ch 8th ch 03627-b - 026 32 32 f i g u re 25. aux i li ar y m o de ti m i ng 30mhz 12.288mhz sharc is always running in slave mode (interrupt driven). fsync-tdm (rfs) rx clk rx data tfs (nc) txclk tx data asdata fstdm bclk dsdata1 sharc ad1839a master mclk dsdata3/aauxdata2 dsdata2/aauxdata1 dlrclk/auxlrclk aauxdata3 dbclk/auxbclk lrclk bclk data mclk dac no. 1 slave dauxdata 03627-b - 027 lrclk bclk data mclk adc no. 3 slave lrclk bclk data mclk adc no. 2 slave lrclk bclk data mclk adc no. 1 slave f i g u re 26. aux i li ar y m o de con n ec t i on (m as ter m o de) to s h a r c
ad1839a rev. b | page 19 of 24 30mhz 12.288mhz sharc is always running in slave mode (interrupt driven). fsync-tdm (rfs) rx clk rx data tfs (nc) txclk tx data asdata fstdm bclk dsdata1 sharc ad1839a slave mclk dsdata3/aauxdata2 dsdata2/aauxdata1 dlrclk/auxlrclk aauxdata3 dbclk/auxbclk lrclk bclk data mclk dac no. 1 slave dauxdata 03627-b - 028 lrclk bclk data mclk adc no. 3 slave lrclk bclk data mclk adc no. 2 slave lrclk bclk data mclk adc no. 1 slave f i g u re 27. aux i li ar y m o de con n ec t i on (slave m o de) to sh a r c contr o l/status registers the ad1839a has 13 co n t r o l r e g i s t ers, 11 o f whic h a r e us e d t o s e t t h e o p er a t ing m o de o f t h e p a r t . th e o t h e r t w o r e g i s t ers, ad c p e a k 0 and a d c p e a k 1, a r e r e ad-o n l y and sh o u ld n o t b e p r og ra mm e d . e a ch o f t h e r e g i s t ers is 10 b i ts wi de w i t h t h e excep t io n o f t h e ad c p e a k r e a d in g r e g i st ers, w h ich a r e 6 b i t s w i d e . w r it i n g to a c o n t ro l re g i st e r re qu i r e s a 1 6 - bit d a t a f r a m e t o b e t r an smi t t e d . bi ts 15 t o 12 a r e t h e addr es s b i ts o f t h e re qu i r e d re g i st e r . bit 1 1 i s a re a d / w r i te bit . bit 1 0 i s re s e r v e d an d s h o u ld al wa ys b e p r og ra mm e d to 0. b i ts 9 t o 0 co n t a i n t h e 1 0 - bi t v a lu e t h a t i s to b e w r it te n to t h e re g i ste r , or , i n t h e c a s e of a r e ad o p er a t ion, t h e 10 -b i t r e g i s t er co n t en t s . f i gur e 15 s h o w s t h e fo r m a t o f t h e s p i r e ad a nd wr i t e op era t io n. dac control r e gisters the ad1839a reg i s t er ma p has eig h t r e g i st ers t h a t a r e us e d t o co n t r o l th e fun c ti o n ali t y o f th e d a c secti o n o f th e pa r t . th e f u n c t i on o f t h e b i ts in t h es e r e g i s t ers is dis c us s e d n e xt. sample rate th e s e b i ts co n t rol t h e s a m p le ra t e o f t h e d a cs. b a s e d o n a 24.576 mh z imclk, s a m p le ra tes o f 48 kh z, 96 kh z, an d 192 kh z a r e a v aila b l e . the m c l k s c alin g b i ts in ad c c o n t r o l 3 s h ou l d b e pro g r a m m e d a ppropr i atel y , b a s e d o n t h e m a s t e r c l o c k fr e q u e n c y . power-dow n / r eset this b i t con t r o ls th e p o w e r - do wn s t a t us o f the d a c s e c t ion. b y d e fa ul t , n o rm al m o de i s se lec t e d ; b y se t t in g th is b i t , th e d i g i tal s e c t io n o f t h e d a c s t a g e can b e p u t in t o a lo w p o w e r m o de , t h us r e d u cin g t h e dig i t a l c u r r en t. th e a n alog o u t p ut s e c t ion o f t h e d a c s t a g e i s n o t p o w e r e d do wn. dac data-wo r d width t h ese tw o b i t s s e t th e w o r d w i d t h o f th e d a c da ta . c o m p a c t d i s k (cd) co m p a t i b ili t y ma y r e q u i r e 16 b i ts, b u t m a n y m o d e r n dig i t a l a u dio fo r m a t s r e q u ir e 24-b i t s a m p le r e s o l u t i o n . dac data for m at the ad1839a s e r i al da t a in t e r f ace can be co nf igur ed t o be co m p a t i b le w i t h a ch o i ce o f p o pu la r in t e r f ace for m a t s, incl uding i 2 s, lj , rj , o r ds p m o des. d e ta il s o n th e s e in t e r f ace m o des a r e p r o v i d e d i n th e se ri a l da ta p o rt s d a ta f o rm a t s e ct i o n . de-emp hasis the ad1839a p r o v ides b u il t-in de-em p hasis f i l t er in g f o r th e thr e e s t anda r d s a m p le ra t e s o f 32.0 kh z, 44.1 kh z, and 48 kh z. mute dac e a c h o f th e six d a cs in the ad1839a has i t s o w n in dep e n d en t m u t e co n t r o l . s e t t in g t h e a p p r o p r i a t e b i t m u t e s t h e d a c o u t p ut. the ad1839a us es a c l ic kles s m u t e f u n c tion t h a t a t t e n u a t es t h e o u t p u t t o a p p r o x ima t e l y ?100 db o v er a n u m b er o f c y c l es. stereo re plicate s e t t i n g th i s b i t co p i e s th e d i g i tal da ta s e n t t o th e s t e r eo pa i r d a c1 t o t h e t h re e o t h e r st er e o d a cs in t h e syst em. this al lo ws al l t h r e e s t er e o d a cs t o b e dr i v en b y o n e dig i t a l da t a s t r e a m . n o t e tha t in th is m o d e , d a c da ta se n t t o th e o t h e r d a cs i s i g nore d. dac volu me control e a c h d a c in t h e ad1839 a has i t s o w n in dep e nden t v o l u m e co n t r o l . the v o l u m e o f each d a c can b e ad j u sted in 1,024 lin e a r st eps b y pr og ra mmin g t h e a p p r o p r i a t e r e g i s t er . the defa u l t val u e f o r this r e g i s t er is 1023, whic h p r o v ides n o a t t e nu at i o n , t h at i s , f u l l v o lu m e .
ad1839a rev. b | page 20 of 24 adc control registers the ad1839a register map has five registers that are used to control the functionality and read the status of the adcs. the function of the bits in each of these registers is discussed below. adc peak level these two registers store the peak adc result from each channel when the adc peak readback function is enabled. the peak result is stored as a 6-bit number from 0 db to ?63 db in 1 db steps. the value contained in the register is reset once it has been read, allowing for continuous level adjustment as required. note that the adc peak level registers use the six most significant bits in the register to store the results. sample rate this bit controls the sample rate of the adcs. based on a 24.576 mhz imclk, sample rates of 48 khz and 96 khz are available. the mclk scaling bits in adc control 3 should be programmed appropriately, based on the master clock frequency. adc power-down this bit controls the power-down status of the adc section and operates in a manner similar to the dac power-down. high-pass filter the adc signal path has a digital high-pass filter. enabling this filter removes the effect of any dc offset in the analog input signal from the digital output codes. adc data-word width these two bits set the word width of the adc data. adc data format the ad1839a serial data interface can be configured to be compatible with a choice of popular interface formats, including i 2 s, lj, rj, or dsp modes. master/slave auxiliary mode when the ad1839a is operating in the auxiliary mode, the auxiliary adc control pins, auxbclk and auxlrclk, which connect to the external adcs, can be set to operate as a master or slave. if the pins are set in slave mode, one of the external adcs should provide the lrclk and bclk signals. adc peak readback setting this bit enables adc peak reading. see the adcs section for more information. table 10. control register map register address register name description type width reset setting (hex) 0000 dacctrl1 dac control 1 r/ w 10 000 0001 dacctrl2 dac control 2 r/ w 10 000 0010 dacvol1 dac volumeleft 1 r/ w 10 3ff 0011 dacvol2 dac volumeright 1 r/ w 10 3ff 0100 dacvol3 dac volumeleft 2 r/ w 10 3ff 0101 dacvol4 dac volumeright 2 r/ w 10 3ff 0110 dacvol5 dac volumeleft 3 r/ w 10 3ff 0111 dacvol6 dac volumeright 3 r/ w 10 3ff 1000 dacvol7 dac volumeleft 4 r/ w 10 3ff 1001 dacvol8 dac volumeright 4 r/ w 10 3ff 1010 adcpeak0 adc left peak r 6 000 1011 adcpeak1 adc right peak r 6 000 1100 adcctrl1 adc control 1 r/ w 10 000 1101 adcctrl2 adc control 2 r/ w 10 000 1110 adcctrl3 adc control 3 r/ w 10 000 1111 reserved reserved r/ w 10 reserved
ad1839a rev. b | page 21 of 24 table 11. dac control 1 function address r/ w res de-emphasis dac data format dac data-word width power-down reset sample rate 15, 14, 13, 12 11 10 9, 8 7, 6, 5 4, 3 2 1, 0 0000 0 0 00 = none 000 = i2s 00 = 24 bits 0 = normal 00 = 8 (48 khz) 01 = 44.1 khz 001 = rj 01 = 20 bits 1 = power-down 01 = 4 (96 khz) 10 = 32.0 khz 010 = dsp 10 = 16 bits 10 = 2 (192 khz) 11 = 48.0 khz 011 = lj 11 = reserved 11 = 8 (48 khz) 100 = packed 256 101 = packed128 110 = reserved 111 = reserved table 12. dac control 2 function mute dac address r/ w res reserved stereo replicate reserved reserved outr3 outl3 outr2 outl2 outr1 outl1 15, 14, 13, 12 11 10 9 8 7 6 5 4 3 2 1 0 0001 0 0 0 0 = off 0 = on 0 = on 0 = on 0 = on 0 = on 0 = on 0 = on 0 = on 1 = replicate 1 = mute 1 = mute 1 = mute 1 = mute 1 = mute 1 = mute 1 = mute 1 = mute table 13. dac volume control function address r/ w res dac volume 15, 14, 13, 12 11 10 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 0010 = dacl1 0 0 0000000000 = mute 0011 = dacr1 0000000001 = 1/1023 0100 = dacl2 0000000010 = 2/1023 0101 = dacr2 1111111110 = 1022/1023 0110 = dacl3 1111111111 = 1023/1023 0111 = dacr3 table 14. adc peak function address r/ w res six data bits four fixed bits 15, 14, 13, 12 11 10 9, 8, 7, 6, 5, 4 3, 2, 1, 0 1010 = left adc 1 0 000000 = 0.0 dbfs 0000 1011 = right adc 000001 = C1.0 dbfs 000010 = C2.0 dbfs these four bits are always 0. 111111 = C63.0 dbfs table 15. adc control 1 function address r/ w res reserved filter adc power- down sample rate reserved 15, 14, 13, 12 11 10 9 8 7 6 5, 4, 3, 2, 1, 0 1100 0 0 0 0 = all pass 0 = normal 0 = 48 khz 0, 0, 0, 0, 0, 0 1 = high-pass 1 = power-down 1 = 96 khz 0, 0, 0, 0, 0, 0
ad1839a rev. b | page 22 of 24 table 16. adc control 2 function adc mute address r/ w res master/slave aux mode adc data format adc data- word width auxdata res right left 15, 14, 13, 12 11 10 9 8, 7, 6 5, 4 3 2 1 0 1101 0 0 0 = slave 000 = i 2 s 00 = 24 bits 0 = off 0 0 = on 0 = on 1 = master 001 = rj 01 = 20 bits 1 = on 1 = mute 1 = mute 010 = dsp 10 = 16 bits 011 = lj 11 = reserved 100 = packed 256 101 = packed 128 110 = auxiliary 256 111 = auxiliary 512 table 17. adc control 3 function address r/ w res res reserved imclk clocking scaling adc peak readback dac test mode adc test mode 15, 14, 13, 12 11 10 9, 8 7, 6 5 4, 3, 2 1, 0 1110 0 0 0, 0 00 = mclk 2 0 = disabled peak readback 000 = normal mode 00 = normal mode 01 = mclk 1 = enabled peak readback all others reserved all others reserved 10 = mclk 2/3 11 = mclk 2 cascade mode dual ad1839a cascade the ad1839a can be cascaded to an additional ad1839a that, in addition to six external stereo adcs and two external stereo dacs, can be used to create a 32-channel audio system with 16 inputs and 16 outputs. the cascade is designed to connect to a sharc dsp and operates in a time division multiplexing (tdm) format. figure 28 shows the connection diagram for cascade operation. the digital interface for both parts must be set to operate in auxiliary 512 mode by programming adc control register 2. ad1839a device 1 is set as the master device by connecting the m /s pin to dgnd; ad1839a device 2 is set as a slave device by connecting the m /s to odvdd. both devices should be run from the same mclk and pd / rst signals to ensure that they are synchronized. with device 1 set as a master, it generates the frame-sync and bit clock signals. these signals are sent to the sharc and device 2, ensuring that both know when to send and receive data. the cascade can be thought of as two 256-bit shift registers, one for each device. at the beginning of a sample interval, the shift registers contain the adc results from the previous sample interval. the first shift register (device 1) clocks data into the sharc and clocks in data from the second shift register (device 2). while this is happening, the sharc is sending dac data to the second shift register. by the end of the sample interval, all 512 bits of adc data in the shift registers have been clocked into the sharc and replaced by dac data, which is subsequently written to the dacs. figure 29 shows the timing diagram for the cascade operation.
ad1839a rev. b | page 23 of 24 alrclk abclk asdata dsdata ad1839a no. 1 (master) sharc (slave) aux adc (slave) dout lrclk bclk aux bclk aux l rclk aux d ata1 aux d ata2 aux d ata3 drx rfsx rclkx tclkx dtx tfsx 03627-b - 029 aux adc (slave) dout lrclk bclk aux adc (slave) dout lrclk bclk alrclk abclk asdata dsdata ad1839a no. 2 (slave) aux adc (slave) dout lrclk bclk aux bclk aux l rclk aux d ata1 aux d ata2 aux d ata3 aux adc (slave) dout lrclk bclk aux adc (slave) dout lrclk bclk f i g u re 28. d u al a d 18 39a cas c ade ad1839a no. 1 dacs l1 l2 l3 l4 r1 r2 r3 r4 ad1839a no. 2 dacs l1 l2 l3 l4 r1 r2 r3 r4 tfsx/ rfsx dtx ad1839a no. 1 adcs l1 l2 l3 l4 r1 r2 r3 r4 ad1839a no. 2 adcs l1 l2 l3 l4 r1 r2 r3 r4 drx msb msb ? 1 lsb bclk dtx msb msb ? 1 lsb drx don?t care 03627-b - 030 256 abclks 32 abclks 256 abclks f i g u re 29. d u al a d 18 39a cas c ade ti ming 5.76k ? 100pf npo a udio input 600z + 47 f 5.76k ? 120pf npo 5.76k ? 5.76k ? 750k ? 1nf npo 237 ? 1nf npo 100pf npo adcxp adcxn 03627-b - 031 op275 v ref v ref op275 237 ? f i g u re 30. t y pic a l a d c input f ilt er c i r c uit 3.01k ? 11k ? 270pf npo 560pf npo 68pf npo 11k ? 150pf npo 1.5k ? 5.62k ? 5.62k ? 604 ? 2.2nf npo v bias (2.25v) outx audio output op275 03627-b - 032 f i g u re 31. t y pic a l da c o u t p ut f ilt er ci rcuit
ad1839a rev. b | page 24 of 24 outline dimensions sea t i n g p l ane view a 2.45 max 1.03 0.88 0.73 t o p v i ew (p i n s d o w n ) 1 39 40 13 14 27 26 52 pin 1 0.65 bsc 13.45 13.20 sq 12.95 7.80 ref 10.20 10.00 sq 9.80 0.40 0.22 7 0 2.20 2.00 1.80 0.13 min coplanarity 0.25 max 10 6 2 0.23 0.11 compliant to jedec standards ms-022-ac. view a rotated 90 ccw f i g u re 32. 5 2 -l ead m e t r ic q u ad f l at p a ckag e [m qfp ] (s-52- 1) di me nsio ns sho w n i n mi ll im e t e r s ordering guide model temperature r a nge package descri ption package option ad1839aas ?40c to +85c 52-lead mqfp s-52-1 ad1839aas-re el ?40c to +85c 52-lead mqfp s-52-1 ad1839aasz 1 ?40c to +85c 52-lead mqfp s-52-1 ad1839aasz-reel 1 ?40c to +85c 52-lead mqfp s-52-1 eval-ad1839 a e b ?40c to +85c 52-lead mqfp s-52-1 1 z = pb-free part. ? 2004 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . c03627C0 C 6/04(b)

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